library ieee; use ieee.std_logic_1164.all; entity logic is port(a,b:in std_logic; c:out std_logic); end logic; architecture a_logic of logic is begin c<=a nor b; end a_logic;
library ieee; use ieee.std_logic_1164.all; entity logic is port(a,b:in std_logic; c:out std_logic); end logic; architecture a_logic of logic is begin c<=a xor b; end a_logic;
XNOR GATE library ieee; use ieee.std_logic_1164.all; entity logic is port(a,b:in std_logic; c:out std_logic); end logic; architecture a_logic of logic is begin c<=not(a xor b); end a_logic;
library ieee; use ieee.std_logic_1164.all; entity logic is port(a:in std_logic; c:out std_logic); end logic; architecture a_logic of logic is begin c<=not a; end a_logic;
library ieee; use ieee.std_logic_1164.all; entity logic is port(a,b:in std_logic; c:out std_logic); end logic; architecture a_logic of logic is begin c<=a or b; end a_logic;
library ieee; use ieee.std_logic_1164.all; entity logic is port(a,b:in std_logic; c:out std_logic); end logic; architecture a_logic of logic is begin c<=a and b; end a_logic;