library ieee;
use ieee.std_logic_1164.all;
entity encoder is
port(y:in std_logic_vector(3 downto 0); a,b : out std_logic);
end encoder;
architecture a_encoder of encoder is
begin
process(y)
begin
case yis
when "1000" => a<='0';b<='0';
when "0100" => a<='0';b<='1';
when "0010" => a<='1';b<='0';
when "0001" => a<='1';b<='1';
when others => null;
end case;
end process;
end a_encoder;
Comments
Post a Comment