library ieee;
use ieee.std_logic_1164.all;
entity fulladder1 is
port(A,B,Cin:in std_logic; sum,carry:out std_logic);
end fulladder1;
architecture FA of fulladder is
begin
sum <= A xor B xor Cin;
carry <= (A and B) or (A and Cin) or (B and Cin);
end FA;
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