library ieee;
use ieee.std_logic_1164.all;
entity mux1 is
port(a,b,c,d:in std_logic; control :in std_logic_vector(1 downto 0); z:out std_logic);
end mux1;
architecture a_mux1 of mux1is
begin
process(a,b,c,d,control)
begin
case control is
when "00" => z<=a;
when "01" => z<=b;
when "10" => z<=c;
when "11" => z<=d;
when others => z<='X';
end case;
end process;
end a_mux1;
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