Basics of Electronics

 library ieee; use ieee.std_logic_1164.all; entity logic is port(a,b:in std_logic; c:out std_logic); end logic; architecture a_logic of logic is begin c<=a nor b; end a_logic;

 library ieee; use ieee.std_logic_1164.all; entity logic is port(a,b:in std_logic; c:out std_logic); end logic; architecture a_logic of logic is begin c<=a xor b; end a_logic;

 XNOR GATE library ieee; use ieee.std_logic_1164.all; entity logic is port(a,b:in std_logic; c:out std_logic); end logic; architecture a_logic of logic is begin c<=not(a xor b); end a_logic;

 library ieee; use ieee.std_logic_1164.all; entity logic is port(a:in std_logic; c:out std_logic); end logic; architecture a_logic of logic is begin c<=not a; end a_logic;

 library ieee; use ieee.std_logic_1164.all; entity logic is port(a,b:in std_logic; c:out std_logic); end logic; architecture a_logic of logic is begin c<=a or b; end a_logic;

 library ieee; use ieee.std_logic_1164.all; entity logic is port(a,b:in std_logic; c:out std_logic); end logic; architecture a_logic of logic is begin c<=a and b; end a_logic;

 library ieee; use ieee.std_logic_1164.all; entity decoder is port(d:in std_logic_vector(1 downto 0); y:out std_logic_vector(3 downto 0)); end decoder; architecture a_decoder of decoder is begin process(d) begin case dis when "00" =>y<="1000"; when "01" =>y<="0100"; when "10" =>y<="0010"; when "11" =>y<="0001"; when others => null; end case; end process; end a_decoder;

 library ieee; use ieee.std_logic_1164.all; entity encoder is port(y:in std_logic_vector(3 downto 0); a,b : out std_logic); end encoder; architecture a_encoder of encoder is begin process(y) begin case yis when "1000" => a<='0';b<='0'; when "0100" => a<='0';b<='1'; when "0010" => a<='1';b<='0'; when "0001" => a<='1';b<='1'; when others => null; end case; end process; end a_encoder;

 library ieee; use ieee.std_logic_1164.all; entity dmux1 is port(z:in std_logic; control :in std_logic_vector(1 downto 0); y:out std_logic_vector(3 downto 0)); end dmux1; architecture a_dmux1 of dmux1 is begin process(control) begin case control is when "00" => y<=z&"000"; when "01" => y<="0"&z&"00"; when "10" => y<="00"&z&"0"; when "11" => y<="000"&z; when others => null; end case; end process; end a_dmux1;

 library ieee; use ieee.std_logic_1164.all; entity mux1 is port(a,b,c,d:in std_logic; control :in std_logic_vector(1 downto 0); z:out std_logic); end mux1; architecture a_mux1 of mux1is begin process(a,b,c,d,control) begin case control is when "00" => z<=a; when "01" => z<=b; when "10" => z<=c; when "11" => z<=d; when others => z<='X'; end case; end process; end a_mux1;

 library ieee; use ieee.std_logic_1164.all; entity fullsubtractor is port(A,B,Cin:in std_logic; borrow,difference:out std_logic); end fullsubtractor; architecture FS of fullsubtractor is begin difference <= A xor B xor Cin; borrow<= (not A and B) or (not A and Cin) or (B and Cin); end FS;

 library ieee; use ieee.std_logic_1164.all; entity fulladder1 is port(A,B,Cin:in std_logic; sum,carry:out std_logic); end fulladder1; architecture FA of fulladder is begin sum <= A xor B xor Cin; carry <= (A and B) or (A and Cin) or (B and Cin); end FA;

 library ieee; use ieee.std_logic_1164.all; entity nand_gate is   port( x,y :in std_logic;           z: out std_logic);         end nand_gate;                  architecture data_nand of nand_gate is         begin           z<=x nand y;         end data_nand;